schematic-plan — independently scanned and version-tracked by SaferSkills.
SaferSkills independently audited schematic-plan (Agent Skill) and scored it 96/100 (green). The audit ran 55 deterministic rules across Security, Supply Chain, Maintenance, Transparency, and Community; it found 0 high-severity and 1 lower-severity findings. The full rule-by-rule trace and per-finding evidence are below. Free, methodology-open.
Findings & checks · 1 flagged
The text {match} tells the agent to skip the normal "ask the user first" gate. Used adversarially it removes the human-in-the-loop check before destructive or sensitive actions, turning a normally-gated agent into a fire-and-forget executor.
Every scanned point with the score it earned and what moved between them.
First recorded scan — no prior version to compare against.
The primary manifest — the file an agent reads to learn what this artifact does.
<CRITICAL-RULE> NEVER use the Read, Write, or Edit tools on KiCad files (.kicad_sch, .kicad_pcb, .kicad_sym, .kicad_mod, .kicad_pro, .kicad_prl). ALL KiCad file manipulation MUST go through the kicad MCP tools. NEVER run kicad-cli commands via Bash. If an MCP tool returns an error, try different parameters — do NOT fall back to manual file editing.
EVERY KiCad operation has a corresponding MCP tool. Do NOT claim a tool does not exist without first listing all available tools. Key tools that MUST be used instead of file writes:
add_symbol — create custom symbol definitions in .kicad_sym filescreate_symbol_library — create new .kicad_sym library filescreate_schematic — create new .kicad_sch filescreate_project — create new .kicad_pro project filesIf you find yourself thinking "there's no MCP tool for this," you are wrong. Check the tool list again. </CRITICAL-RULE>
Pure planning phase — no file modifications. Only inspection MCP tools (list_lib_symbols, get_symbol_info). Note: get_symbol_pins requires a schematic with placed symbols and cannot be used during planning. Use get_symbol_info instead — it reads pin definitions directly from library files.
Inputs: specs/bom.md (validated BOM from circuit-design) Outputs: specs/schematic-plan.md (placement and wiring plan)
When this skill activates, print exactly:
Using schematic-plan to plan placement and wiring from the validated BOM.
Then immediately proceed to the Pre-flight checks. This is a mechanical planning phase — do not ask the user what to do. Read specs/bom.md and execute the planning steps.
Report progress at natural milestones (after page size calculation, after coordinate assignment, after wiring plan). Keep status updates to one line each.
specs/bom.md existsvalidate_hierarchy to inspect current annotation state — the plan must account for existing ref conflicts
Count components per stage. Estimate space using spacing rules:
Calculate total bounding box. Pick smallest standard page that fits. Record decision and math explicitly (show the arithmetic).
Standard page sizes (landscape):
| Size | Width (mm) | Height (mm) | Usable W | Usable H |
|---|---|---|---|---|
| A4 | 297 | 210 | 179 | 168 |
| A3 | 420 | 297 | 302 | 255 |
| A2 | 594 | 420 | 476 | 378 |
Usable W = width - 20 (margins) - 108 (title block width near bottom-right). Usable H = height - 20 (margins) - 32 (title block height).
Assign each functional stage a bounding box on the sheet:
## Stage Layout
| Stage | Bounding Box | Components |
|-------|-------------|------------|
| Input protection | (25, 50) -> (140, 90) | J1, F1, D1, C1, C2, Q1, D3, R5 |
| Buck converter | (25, 115) -> (240, 170) | U1, C3, C4, ... |Assign exact (x, y) per component within its stage bounding box:
## Placement
| Ref | lib_id | x | y | rotation | Stage |
|-----|--------|---|---|----------|-------|
| J1 | Connector_Generic:Conn_01x02 | 25.4 | 50.8 | 0 | Input protection |For each net, specify tool and connections. Available tools:
connect_pins — direct Manhattan wire between two adjacent pinswire_pins_to_net — connect one or more pins to a named net labelGroup all pins for the same net into a single wire_pins_to_net call. Do not make separate calls for individual pins on the same net. Wiring order follows table order top-to-bottom; list power nets before signal nets.
## Wiring
| Order | Net | Tool | Pins |
|-------|-----|------|------|
| 1 | J1:1 -> F1:1 | connect_pins | Direct, adjacent |
| 2 | VIN | wire_pins_to_net | F1:2, D1:K, C1:1, C2:1, Q1:S, D3:K |
| 3 | PGND | wire_pins_to_net | J1:2, D1:A, C1:2, C2:2, R5:2 |List pins needing no-connect flags and nets needing PWR_FLAG.
## No-Connect Pins
| Ref | Pin | Reason |
|-----|-----|--------|
| U1 | NC | Unused pin per datasheet |
## Power Flags
| Net | Reason |
|-----|--------|
| VOUT | Regulator output, not recognized as power source by KiCad |If the design requires multiple sheets, plan sheet boundaries and hierarchical labels here.
These are the ONLY kicad MCP tools you should use during planning (inspection only — no modifications):
Symbol and footprint lookup:
list_lib_symbols — verify symbol exists in libraryget_symbol_info — get pin names, types, and propertieslist_lib_footprints — verify footprint existsget_footprint_info — check pad dimensionsSchematic inspection (if schematic already exists):
get_schematic_summary — get item counts for a sheetlist_schematic_components — list symbols on a sheetlist_schematic_labels — list net labels on a sheetlist_schematic_wires — list wires on a sheetlist_schematic_global_labels — list global labels on a sheetlist_schematic_hierarchical_labels — list hierarchical labels on a sheetlist_schematic_sheets — list hierarchical sheet blocks on a sheetlist_schematic_junctions — list junctions on a sheetlist_schematic_no_connects — list no-connect flags on a sheetlist_schematic_bus_entries — list bus entries on a sheetis_root_schematic — check if a schematic is root or sub-sheetlist_hierarchy — view the full sheet hierarchy treeget_sheet_info — get sheet details with pin/label matching statusvalidate_hierarchy — check for orphaned labels/pins, direction mismatches, duplicate refsRun validate_hierarchy before planning to understand existing annotation state. If it reports duplicate_ref or unannotated_ref, the plan should include an annotation step.
list_cross_sheet_nets — list all nets crossing sheet boundariesget_symbol_instances — list symbol instances from root schematictrace_hierarchical_net — trace a net across the hierarchy to understandexisting cross-sheet connections before planning new ones
Do NOT use get_symbol_pins — it requires a placed schematic. Use get_symbol_info instead.
After writing specs/schematic-plan.md, dispatch the schematic plan reviewer subagent:
Agent(
prompt="<contents of agents/schematic-plan-reviewer.md>\n\nPlan path: <project_dir>/specs/schematic-plan.md\nBOM path: <project_dir>/specs/bom.md",
subagent_type="general-purpose"
)Fix any issues reported by the reviewer, update specs/schematic-plan.md, and re-dispatch until the reviewer returns APPROVED.
<HARD-GATE> User must explicitly approve the plan before schematic-design can start. "The coordinates look reasonable" is not approval — the reviewer must have returned APPROVED first. </HARD-GATE>
User rejection handling: If the user rejects the plan or requests changes (e.g., different stage layout, different page size), fix the specific issues and re-run the schematic plan reviewer.
IMPORTANT: Use TodoWrite to create todos for EACH checklist item below.
specs/bom.md exists and is APPROVEDspecs/schematic-plan.md artifact| Thought | Reality |
|---|---|
| "A4 is big enough" | Show the math. Components * spacing + margins + title block. |
| "These coordinates look right" | Check every Y < page_height - margin, every X < page_width - margin. |
| "I know this pin name" | Call get_symbol_info. Don't guess pin names from memory. |
| "The spacing is fine" | Minimum 10.16mm vertical, 12.7mm horizontal. Measure, don't eyeball. |
mkdir -p skills/schematic-plangit commit -m "feat: add schematic-plan skill for placement and wiring planning" (NO Co-Authored-By)~30 seconds. Free. No account. Every finding cites a rule and a line of evidence.