fpga-synthesis-fit — independently scanned and version-tracked by SaferSkills.
SaferSkills independently audited fpga-synthesis-fit (Agent Skill) and scored it 100/100 (green). The audit ran 55 deterministic rules across Security, Supply Chain, Maintenance, Transparency, and Community; it found 0 high-severity and 0 lower-severity findings. The full rule-by-rule trace and per-finding evidence are below. Free, methodology-open.
Findings & checks · 0 flagged
Every scanned point with the score it earned and what moved between them.
First recorded scan — no prior version to compare against.
The primary manifest — the file an agent reads to learn what this artifact does.
Getting RTL to fit and route on an FPGA is a measurement problem before it is an optimization problem. The tools report several different "area" numbers and most of them lie about what will actually fit. Optimizing against the wrong number burns hours and can make the real result worse.
Core principle: Judge fit and timing by the post-pack, post-place numbers (nextpnr TRELLIS_COMB and the critical-path report), never by the synthesis-stage estimate. Measure with data before you change RTL.
yosys stat after synth_ecp5 reports LUT4, which is pre-pack. nextpnr reports TRELLIS_COMB, which is post-pack (LUT4 plus PFUMX, L6MUX21, and carry packed into slices). These differ, sometimes a lot.
A change that cuts LUT4 can be neutral or worse for TRELLIS_COMB. Replacing a barrel shifter with a mux tree is the classic example: barrel shifters pack densely into carry chains, mux trees spread into PFUMX/L6MUX. Always judge by the nextpnr Device utilisation: TRELLIS_COMB line. An 80% pre-pack can be a 91% post-pack that won't route.
TRELLIS_COMB. At 89 to 91% it can churn for an hour or two, sometimes never converging. Around 80% routes in minutes.yosys memory inference (memory_bram) from generic RTL is unreliable, especially with an init value plus a write port plus read latency. It falls back to flops or maps wrong. For ROMs and RAMs, instantiate the primitive (DP16KD on ECP5) directly.
The flop-ROM trap: a ROM built as a register array with per-entry reset values (a RegisterFile(resetValue: contents)) synthesizes to a giant flop array plus an N:1 read mux, not block RAM, because per-entry reset can't map to BRAM (BRAM init comes from the bitstream, not reset). A 679x139 ROM becomes about 94k flops, four times a whole LFE5U-25F. Always check whether your "ROM" is actually flops; the yosys generic stat shows it as N $sdffe. Fix with an explicit DP16KD carrying INITVAL.
See dp16kd-initval-packing.md in this skill directory for the exact INITVAL bit layout and the port mapping. Derive packing from yosys's own brams_map_16kd.v; do not reinvent it. The DP16KD registered read IS your read-pipeline stage, so don't add a separate one. Keep a flop fallback for simulation at the same read latency, since you can't sim a DP16KD blackbox honoring INITVAL.
synth_ecp5 with abc9 can take over an hour on a big design. -noabc9 inflates LUT counts four to eight times (unfittable, useless for judging fit). Neither full path is quick.synth_ecp5 (abc9 is fine on a single module, minutes) and read its mapped TRELLIS_COMB. Caveat: a module synthed standalone with undriven inputs lets opt prune most of it, reporting a misleading near-zero. For in-context size, run the full-design generic stat (read, hierarchy, proc, opt -fast, stat, no abc9) and read per-module cell counts and $mux/$add to find the giant and its type (mux-bound vs arithmetic vs memory).nextpnr-ecp5 --freq <target>, read "Max frequency for clock". The output XOR adds a little artificial depth, so it slightly under-reports; fine for relative comparison.rtl-area-timing.The PLL output, the UART baud divisor, and the timer timebase all derive from the configured clock frequency. If the logic only meets 29 MHz, you must regenerate the bitstream at a clock at or below Fmax (24 MHz, say). Running a 48-MHz-configured bitstream on hardware that only times at 29 MHz fails with setup violations AND a wrong baud rate. Pick a clean integer PLL divide (48/24 = 2).
ecppack lives in prjtrellis (nixpkgs trellis), often not in the same shell as yosys/nextpnr. Bring it in separately.nextpnr --timing-allow-fail lets P&R finish and emit a config/bitstream even when timing fails the constraint, useful to get a bit running at a lower real clock.creek core was fit to a 25F by working these numbers (208% to 88.5% post-pack).nix-eda-packaging).rtl-area-timing, fpga-bringup, and rohd-rtl-gotchas.~30 seconds. Free. No account. Every finding cites a rule and a line of evidence.