differential-verification — independently scanned and version-tracked by SaferSkills.
SaferSkills independently audited differential-verification (Agent Skill) and scored it 100/100 (green). The audit ran 55 deterministic rules across Security, Supply Chain, Maintenance, Transparency, and Community; it found 0 high-severity and 0 lower-severity findings. The full rule-by-rule trace and per-finding evidence are below. Free, methodology-open.
Findings & checks · 0 flagged
Every scanned point with the score it earned and what moved between them.
First recorded scan — no prior version to compare against.
The primary manifest — the file an agent reads to learn what this artifact does.
You trust a design by running it against something you already trust and comparing. The DUT (device under test) executes a stimulus; a golden reference model executes the same stimulus; you compare the resulting state. A mismatch is a bug in one of them, and finding which is the work.
Core principle: Same stimulus, two executors, compare state. Everything else (fuzzing, coverage, campaigns) exists to generate good stimulus and to localize the divergence. The comparison is only as good as the state you capture and how honestly you name it.
generate stimulus -> run on DUT -> capture DUT state
-> run on golden model -> capture golden state
-> compare -> divergence? report : record coveragefalse is a false pass waiting to happen. Make sure a captured value is actually compared.Capture and compare register state under raw hardware names: x0..x31, pc, raw CSR names. ABI aliases (a0, ra, sp) are a rendering concern for the frontend only. If the comparison layer speaks ABI names, two tools will eventually disagree about which physical register a0 is and you'll chase a phantom mismatch.
Random stimulus plateaus fast. Close the loop with coverage:
fpga-synthesis-fit.Track coverage on both the simulator and the silicon. When the same stimulus exercises different coverage on the two, that divergence is a finding in its own right, even before an architectural state mismatch shows up. An optional strict mode can flip the verdict on coverage divergence alone.
When state mismatches:
| Smell | Do instead |
|---|---|
| Reading a value but recording it as absent/false | Verify captured fields are actually compared |
| State keyed by ABI names | Key by hardware names, render ABI on the frontend |
| Pure random fuzzing | Coverage-guided with a novelty scheduler |
| Only comparing final state | Find the first diverging step |
| Assuming the golden model is correct | Localize, then decide which side is wrong |
| Strict checks toggled off to get a pass | Fix the divergence; see silicon-grade-discipline |
| Test checks only that the transaction completed | Assert the read-back data, not just the handshake |
| Model ignores byte-enables or leaves DQ/DQS as X | Compare on a channel-faithful model or on hardware |
| Blaming silicon before the emulator ran | Reproduce on a golden model with perfect memory first |
| Two "identical" builds differ, editing RTL | FASM-diff the bitstreams; byte-identical means a physical difference |
| Rebuilding the toolchain on a theorized root cause | Validate a cheap fix empirically first; the cause may be secondary |
| Testing writes and reads together on a dead lane | Bisect with a read-only oracle (DDR MPR or pre-written pattern) |
x0..x31/pc/raw CSR; ABI names are render-only.rtl-area-timing.sim-honesty-and-false-passes.md in this directory: the false-pass modes (a model that drops byte-enables or DQ/DQS, an ACK-liveness-only test), the variance-vs-determinism rule that tells metastability from a logic bug, reproducing on perfect memory to exonerate the hardware, why a paced debug probe can lie, FASM-diffing two "identical" builds (byte-identical means a physical difference), validating a cheap fix before a toolchain rebuild, and bisecting a dead DDR lane with a read-only MPR oracle.codegen-validation (which uses this loop on generated code) and fpga-bringup.~30 seconds. Free. No account. Every finding cites a rule and a line of evidence.