openocd-jlink-stlink-debug — independently scanned and version-tracked by SaferSkills.
SaferSkills independently audited openocd-jlink-stlink-debug (Agent Skill) and scored it 100/100 (green). The audit ran 55 deterministic rules across Security, Supply Chain, Maintenance, Transparency, and Community; it found 0 high-severity and 0 lower-severity findings. The full rule-by-rule trace and per-finding evidence are below. Free, methodology-open.
Findings & checks · 0 flagged
Every scanned point with the score it earned and what moved between them.
First recorded scan — no prior version to compare against.
The primary manifest — the file an agent reads to learn what this artifact does.
Use this skill to debug probe sessions by separating physical wiring, probe firmware, target voltage, reset strategy, transport, target script, flash algorithm, and GDB behavior. Probe failures are often reset or adapter issues.
Use this skill when:
OpenOCD, J-Link, ST-Link, CMSIS-DAP, pyOCD, or GDB.
scripts, flash loaders, protected devices, semihosting, RTT, or multicore.
Do not use this skill for application fault analysis after a stable debug session exists. Use the architecture-specific debug skill then. For flash download failures focused on erase/program/verify, use mcu-flashing-debug.
Ask for:
VTref, GND, SWDIO/TMS, SWCLK/TCK, nRST/SRST, SWO, andpower ownership.
-f interface/*.cfg and -f target/*.cfg scripts,adapter speed, transport select, and full log.
RDP), low-power state, andexternal flash.
openocd -f interface/stlink.cfg -f target/stm32f4x.cfg(stlink.cfg is the hla driver; use target/stm32f1x.cfg, stm32h7x.cfg, nrf52.cfg etc. for other parts).
openocd -f interface/jlink.cfg -c "transport select swd" -f target/stm32f4x.cfg.openocd -f interface/cmsis-dap.cfg -c "transport select swd" -f target/stm32f1x.cfg.-c "transport select jtag" (note stlink.cfghla only supports hla_swd/hla_jtag).
-c "adapter speed 1000" (kHz; deprecatedalias adapter_khz). Pick a probe by serial with -c "adapter serial <SN>" (older: hla_serial).
3333, Telnet monitor 4444, Tcl 6666.Check VTref, ground, cable length, pinout, SRST line, and whether the probe powers or only senses the target. In the log confirm a valid SWD DPIDR 0x2ba01477 (Cortex-M3/M4) or JTAG IDCODE, not a zero/failed read (SWD DPIDR 0x00000000 / Error connecting DP: cannot read IDR).
Start with adapter speed 480 or lower, then raise only after IDCODE, halt, reset, and mdw reads are stable.
In the target/board cfg set reset_config, e.g. srst_only srst_nogate for connect-under-reset, or none separate. Then use reset halt / reset init / reset run. Add -c "reset_config connect_assert_srst" for locked or fast-sleeping parts.
Confirm transport select, chip family cfg, TAP/DAP IDs (-expected-id on jtag newtap/swj_newdap, -dp-id for SWD multidrop), flash bank, and _TARGETNAME/work-area RAM. List cores with targets.
Enter the monitor with telnet localhost 4444, then init and reset halt. Read state with targets, reg, mdw 0x08000000 4, mdh, mdb; write with mww 0x40021000 0x01. Only then flash: program firmware.elf verify reset or flash write_image erase firmware.bin 0x08000000 / flash erase_sector 0 0 last / flash info 0. resume to run, dump_image out.bin 0x08000000 0x10000 to read back.
Enable arm semihosting enable, SWO/tpiu, or RTT only after the base debug path is reliable (see RTT And Semihosting).
arm-none-eabi-gdb firmware.elf
(gdb) target extended-remote localhost:3333
(gdb) monitor reset halt
(gdb) load
(gdb) monitor reg
(gdb) continueUse target remote for a single-session attach, target extended-remote to allow reconnect. monitor <cmd> forwards any OpenOCD command (e.g. monitor reset init, monitor flash write_image erase firmware.bin).
arm semihosting enable (optionallyarm semihosting_fileio enable); printf/puts output appears on the OpenOCD console once the firmware links libnosys/semihosting stubs.
rtt setup 0x20000000 2048 "SEGGER RTT" then rtt start; expose achannel with rtt server start 9090 0 and read it via telnet localhost 9090. Use rtt channels to confirm the control block was found. The ID string defaults to "SEGGER RTT".
VTref is missing, so Error: target voltage may be too low or the probecannot sense target voltage.
DPIDR read (Error connecting DP: cannot read IDR), Error: init mode failed (unable to connect to the target), or SWD ack not OK.
SRST not wired but the script uses reset_config srst_only; switch tonone/connect_assert_srst.
Error: … cannot be programmed); forSTM32 clear RDP with stm32f4x unlock 0 / stm32f1x unlock 0 (mass-erases).
flash bank or work-area RAM, soflash write_image/program fails or verify mismatches.
flash bank driver(stmqspi, cfi), not the internal loader.
hla (stlink.cfg) cannot do raw swd/jtag low-level commands or SWDmultidrop; use interface/stlink-dap.cfg or a J-Link/CMSIS-DAP v2 probe.
Before claiming the debug path works:
transport, adapter speed, and reset mode.SWD DPIDR/IDCODE, reset halt, targets shows halted, a regread, and an mdw memory read.
program … verify reset or flash write_image plus verify whenflashing is required.
reset run and power-cycle, i.e.after debugger-specific settings.
User:
OpenOCD 连 STM32 一直 timeout。Agent:
VTref, ground, SWD pins, SRST, and lowers adapter speed 480.reset_config connect_assert_srst and the correcttarget/stm32f4x.cfg, watching for SWD DPIDR.
init, targets, mdw) fromprogram/flash write_image errors.
~30 seconds. Free. No account. Every finding cites a rule and a line of evidence.